Header Standard de gestion des périphériques
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Pour les 'Mots entiers', les valeurs correspondent aux valeurs que l'on utilise pour former le mot. Une valeur ou 0 doit être pris sur chaque ligne, ou entre chaque signe '|'

Controle du BUS (exemple : BUS_ADDR->exp_gcontrol=0;)

Registre
 Désignation
Reset Value
Valeurs
BUS_ADDR->prim_gcontrol
Contrôle
Bus primaire
Mot entier
  

HOLDST | NOHOLD | HIZ
EXTERNAL_RDY,INTERNAL_RDY,OR_EXT_INT,AND_EXT_INT
WS_0,WS_1,WS_2,WS_3,WS_4,WS_5,WS_6,WS_7
BANK_16M,...,BANK_1M,BANK_512K,...,BANK_1K,BANK_512,BANK_256
BUS_ADDR->prim_gcontrol_bit.bnkcmp BNKCMP 256 octets Bank compare This 5-bit field specifies the number of MSBs of the address to be used to define the bank size.
BANK_SIZE_16M,...,BANK_SIZE_1M,BANK_SIZE_512K,...,BANK_SIZE_1K,
BANK_SIZE_512,...,BANK_SIZE_256
BUS_ADDR->prim_gcontrol_bit.hiz HIZ 0 Internal hold When set (HIZ = 1), the port is put in hold mode. This is equivalent to the external HOLD signal. By forcing the high-impedance condition, the ’C3x can relinquish the external memory port through software. HOLDA goes low when theport is placed in the high impendance state. (STRB0 control register only)
BUS_ADDR->prim_gcontrol_bit.holdst HOLDST 0 Hold status bit This bit signals whether the port is being held (HOLDST = 1), or is not being held (HOLDST = 1). This status bit is valid whether the port has been held through hardware or software.(STRB0 control register only)
BUS_ADDR->prim_gcontrol_bit.nohold NOHOLD 0 Port hold signal NOHOLD allows or disallows the port to be held by an external HOLD signal. When NOHOLD = 1, the ’C3x takes over the external bus and controls it, regardless of serviced or pending requests by external devices. No hold acknowledge (HOLDA) is asserted when a HOLD is received. However, it is asserted if an internal hold is generated (HIZ = 1). (STRB0 control register only)
BUS_ADDR->prim_gcontrol_bit.sww SWW Ext
&Int Ready		 Software wait mode In conjunction with WTCNT, this 2-bit field defines the mode
of wait-state generation.
EXT_RDY,INT_RDY,OR_RDY(Int or Ext),AND_RDY(Int & Axt)
BUS_ADDR->prim_gcontrol_bit.wtcnt WTCNT 7 WS Software wait mode This 3-bit field specifies the number of cycles to use when
in the software wait mode for the generation of internal wait state. The range is 0 (WTCNT = 0 0 0) to 7 (WTCNT = 111) H1/H3 cycles.
WAIT_0,WAIT_1,WAIT_2,WAIT_3,WAIT_4,WAIT_5,WAIT_6,WAIT_7
BUS_ADDR->exp_gcontrol
Contrôle Bus Extension
   EXTERNAL_RDY,INTERNAL_RDY,OR_EXT_INT,AND_EXT_INT
WS_0,WS_1,WS_2,WS_3,WS_4,WS_5,WS_6,WS_7
BUS_ADDR->exp_gcontrol_bit.sww   Ext
&Int Ready		 Software wait mode
EXT_RDY,INT_RDY,OR_RDY(Int or Ext),AND_RDY(Int & Axt)
BUS_ADDR->exp_gcontrol_bit.wtcnt   7 WS Software wait mode
WAIT_0,WAIT_1,WAIT_2,WAIT_3,WAIT_4,WAIT_5,WAIT_6,WAIT_7

DMA-Control Registers(exemple : DMA_ADDR->gcontrol_bit.start=START0;)

Registre
 Désignation
Reset Value
Valeurs
DMA_ADDR->gcontrol
DMA Global Control Register
Mot entier
  

START0,START1,START2,START3
STAT0,STAT1,STAT2,STAT3
INCSRC | DECSRC | INCDST | DECDST
SYNC0 | SYNC1 | SYNC2 | SYNC3

DMA_ADDR->gcontrol_bit.decsrc DECSRC 0 DMA source address decrement mode If DECSRC = 1, the source address is decremented after every read. If INCSRC = DECSRC, the source address is not modified after a read.
DMA_ADDR->gcontrol_bit.decdst DECDST 0 DMA destination address decrement mode If DECDST = 1, the destination address is decremented after every write.If INCDST = DECDST, the destination address is not modified after a write.
DMA_ADDR->gcontrol_bit.incdst INCDST 0 DMA destination address increment mode If INCDST = 1, the destination address is incremented after every write.
DMA_ADDR->gcontrol_bit.incsrc INCSRC 0 DMA source address increment mode If INCSRC = 1, the source address is incremented after every read.
DMA_ADDR->gcontrol_bit.start START START0 DMA start control Controls the state in which the DMA starts and stops. The DMA may be stopped without any loss of data. The following table summarizes the START bits and DMA operation:
0 read or write cycles in progress are completed; any data read is ignored. Any pending read or write is cancelled. The DMA is reset so that when it starts, a new transaction begins; that is, a read is per-formed
1 If a read or write has begun, it is completed before it stops. If a read or write has not
begun, no read or write is started.
2 If a DMA transfer has begun, the entire transfer is complete (including both read
and write operations) before stopping. If a transfer has not begun, none is started.
3 DMA starts from reset or restarts from the previous state.
When the DMA completes a transfer, the START bits remain in START3. The DMA starts when the START bits are set to START3 and one of the following conditions applies:
The transfer counter is set to a value different from 0x0 OR The TC bit is set to 0.
DMA_ADDR->gcontrol_bit.stat STAT STAT0 DMA status Indicates the status of the DMA and changes every cycle. The following table summarizes the STAT bits and DMA status.
0 The DMA is being held between DMA transfer (between a write and a read).
1 DMA is being held in the middle of a DMA transfer (between a read and a write).
2 Reserved.
3 DMA busy. DMA is performing a read or write or waiting for a source or destination synchronization interrupt.
DMA_ADDR->gcontrol_bit.sync SYNC SYNC0 DMA synchronization mode Determines the timing synchronization between the events initiating the source and destination transfers. The following table summarizes the SYNC bits and DMA synchronization.
0 No synchronization. Enabled interrupts are ignored (reset value).
1 Source synchronization. A read is per-formed when an enabled interrupt occurs.
2 Destination synchronization. A write is per-formed when an enabled interrupt occurs.
3 Source and destination synchronization. A read is performed when an enabled interrupt occurs. A write is then performed when the next enabled interrupt occurs.
DMA_ADDR->gcontrol_bit.tc
TC
 0 DMA transfer mode Affects the operation of the transfer counter. If TC = 0, transfers are not terminated when the transfer counter becomes 0. If TC = 1, transfers are terminated when the transfer counter becomes 0.
DMA_ADDR->gcontrol_bit.tcint TCINT 0 DMA transfer counter interrupt mode If TCINT = 1, the DMA interrupt is set when the transfer
counter makes a transition to 0. If TCINT = 0, the DMA interrupt is not set when the transfer counter makes a transition to 0.
DMA_ADDR->source   0 DMA 0 Source Address
DMA_ADDR->destination   0 DMA 0 Destination Address
DMA_ADDR->transfer_counter   0 DMA 0 Transfer Counter The transfer-counter register is a 24-bit register that contains the number of words to be transmitted.

Serial-Port-Control Registers (exemple : SERIAL_PORT_ADDR(n)->gcontrol=START0;)

Registre
 Désignation
Reset Value
Valeurs
SERIAL_PORT_ADDR(n)->gcontrol
Global Control Register
   RRDY | XRDY | FSXOUT | XSREMPTY | RSRFULL | HS | XCLKSRCE | RCLKSRCE | XVAREN | RVAREN | XFSM | RFSM | CLKXP | CLKRP | DXP | DRP | FSXP | FSRP
XLEN_8,XLEN_16,XLEN_24,XLEN_32
RLEN_8,RLEN_16,RLEN_24,RLEN_32
XTINT | XINT | RTINT | RINT | XRESET | RRESET
SERIAL_PORT_ADDR(n)->gcontrol_bit.clkrp CLKR 0 CLKR polarity If CLKRP = 0, CLKR is active (high). If CLKRP = 1, CLKR is active (low).
SERIAL_PORT_ADDR(n)->gcontrol_bit.clkxp CLKX 0 CLKX polarity If CLKXP = 0, CLKX is active high. If CLKXP = 1, CLKX is active low.
SERIAL_PORT_ADDR(n)->gcontrol_bit.drp DRP 0 DR polarity If DRP = 0, DR is active (high). If DRP = 1, DR is active (low).
SERIAL_PORT_ADDR(n)->gcontrol_bit.dxp DXP 0 DX polarity If DXP = 0, DX is active (high). If DXP = 1, DX is active (low).
SERIAL_PORT_ADDR(n)->gcontrol_bit.fsrp FSRP 0 FSR polarity If FSRP = 0, FSR is active (high). If FSRP = 1, FSR is active (low).
SERIAL_PORT_ADDR(n)->gcontrol_bit.fsxp FSXP 0 FSX polarity If FSXP = 0, FSX is active (high). If FSXP = 1, FSX is active (low).
SERIAL_PORT_ADDR(n)->gcontrol_bit.fsxout FSXOUT   Transmit frame sync configuration FSXOUT = 0 configures the FSX pin as an input. FSXOUT = 1 configures the FSX pin as an output.
SERIAL_PORT_ADDR(n)->gcontrol_bit.hs HS 0 Handshake If HS = 1, the handshake mode is enabled. If HS = 0, the handshake mode is disabled.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rclksrce RCLK_SRCE 0 Receive clock source If RCLK SRCE = 1, the internal receive clock is used. If RCLK SRCE = 0, the external receive clock is used.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rfsm RFSM 0 Receive frame sync mode Configures the port for continuous mode operation or standard
mode operation.If RFSM = 1 (continuous mode), only the first word of a block generates a sync pulse, and the rest are received continuously to the end of the block.
If RFSM = 0 (standard mode), each word received has an associated sync pulse.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rint RINT 0 Receive interrupt enable If RINT = 0, the receive interrupt is disabled. If RINT = 1, the receive interrupt is enabled. Note: The CPU receive interrupt flag RINT and the serial-port-
to-DMA interrupt (ERINT0 in the IE register) are the OR of the enabled receive timer interrupt and the enabled receive interrupt.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rlen RLEN 8 bits Receive word length These two bits define the word length of serial data received.
All data is right justified in the receive buffer.
EIGHT_BITS,SIXTEEN_BITS,TWENTY_FOUR_BITS,THIRTY_TWO_BITS
SERIAL_PORT_ADDR(n)->gcontrol_bit.rrdy RRDY 0 Receive ready flag If RRDY = 1, the receive buffer has new data and is ready to be read. A three H1/H3 cycle delay occurs from the loading of DRR to RRDY = 1. The rising edge of this signal sets RINT. If RRDY = 0, the receive buffer does not have new data since the last read. RRDY = 0 at reset and after the receive buffer is read.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rreset RRESET 0 Peripherals Receive reset If RRESET = 0, the receive side of the serial port is reset.
To take the receive side of the serial port out of reset, set RRE-SET to 1.
Do not set RRESET to 1 until at least three cycles after RESET goes inactive. This applies only to system reset. Setting RRESET to 0 does not change the contents of any of the serial-port control registers. It places the receiver in a state corresponding to the beginning of a frame of data. Reset this bit at the same time that the mode of the receiver is set. You can toggle without resetting the global-control register.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rsrfull RSRFULL 0 Receive-shift register full flag If RSRFULL = 1, an overrun of the receiver has occurred. In
continuous mode, RSRFULL is set to 1 when both RSR and DRR are full. In noncontinuous mode, RSRFULL is set to 1 when RSR and DRR are full and a new FSR is received. A read causes this bit to be set to 0. This bit can be set to 0 only by a system reset, a serial-port receive reset (RRESET = 1), or a read. When the receiver tries to set RSRFULL to 1 at the same time that the global register is read, the receiver dominates, and RSRFULL is set to 1. If RSRFULL = 0, no overrun of the receiver has occurred.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rtint RTINT 0 Receive timer interrupt enable If RTINT = 0, the receive timer interrupt is disabled. If RTINT = 1, the receive timer interrupt is enabled.
SERIAL_PORT_ADDR(n)->gcontrol_bit.rvaren RVAREN 0 Receive data rate mode Specifies a fixed or variable data rate mode when receiving. If RVAREN = 0 (fixed data rate), FSX is active for at least one RCLK cycle and then goes inactive before reception begins. If RVAREN = 1 (controlled data rate), FSX is active while all bits are being received.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xclksrce XCLK SRCE 0 Transmit clock source If XCLK SRCE = 1, the internal transmit clock is used. If XCLK SRCE = 0, the external transmit clock is used.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xfsm XFSM 0 Transmit frame sync mode Configures the port for continuous mode operation or standard
mode operation. If XFSM = 1 (continuous mode), only the first word of a block generates a sync pulse, and the rest are transmitted continuously to the end of the block.
If XFSM = 0 (standard mode), each word has an associated sync pulse.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xint XINT 0 Transmit interrupt enable If XINT = 0, the transmit interrupt is disabled. If XINT = 1, the transmit interrupt is enabled. Note: The CPU receive flag XINT and the serial-port-to-DMA interrupt (EXINT0 in the IE register) is the OR of the enabled transmit timer interrupt and the enabled transmit interrupt.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xlen XLEN 8 bits Transmit word length These two bits define the word length of serial data trans-mitted. All data is assumed to be right justified in the transmit buffer when fewer than 32 bits are specified.
EIGHT_BITS,SIXTEEN_BITS,TWENTY_FOUR_BITS,THIRTY_TWO_BITS
SERIAL_PORT_ADDR(n)->gcontrol_bit.xrdy XRDY 1 Transmit ready flag If XRDY = 1, the transmit buffer has written the last bit of data to the shifter and is ready for a new word. A three H1/H3 cycle delay occurs from the loading of the transmit shifter until XRDY is set to 1. The rising edge of this signal sets XINT. If XRDY = 0, the transmit buffer has not written the last bit of data to the transmit shifter and is not ready for a new word.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xreset XRESET 0 Transmit reset If XRESET = 0, the transmit side of the serial port is reset. To take the transmit side of the serial port out of reset, set XRESET to 1. Do not set XRESET to 1 until at least three cycles after RESET goes inactive. This applies only to system reset. Setting XRESET to 0 does not change the contents of any of the serial-port control registers. It places the transmitter in a state corresponding to the beginning of a frame of data. Resetting the transmitter generates
a transmit interrupt. Reset this bit during the time the mode of the transmitter is set. You can toggle XFSM without resetting the global-control register.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xsrempty XSREMPTY 0 Transmit-shift register empty flag If XSREMPTY = 0, the transmit-shift register is empty. If XSREMPTY = 1, the transmit-shift register is not empty. Reset or XRESET causes this bit to = 0.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xtint XTINT 0 Transmit timer interrupt enable If XTINT = 0, the transmit timer interrupt is disabled. If XTINT = 1, the transmit timer interrupt is enabled.
SERIAL_PORT_ADDR(n)->gcontrol_bit.xvaren XVAREN 0 Transmit data rate mode Specifies a fixed or variable data rate mode when transmitting. With a fixed data rate, FSX is active for at least one XCLK cycle and then goes inactive before transmission begins. With variable data rate, FSX is active while all bits are being transmitted. When you use an external FSX and variable data rate signaling, the DX pin is driven by the transmitter when FSX is held active or when a word is being shifted out.
SERIAL_PORT_ADDR(n)->s_r_control
FSR/DR/CLKR Port Control Register
 0 CLKRFUNC | CLKRI_O | CLKRDATOUT | CLKRDATIN | DRFUNC | DRI_O | DRDATOUT | DRDATIN | FSRFUNC | FSRI_O | FSRDATOUT | FSRDATIN
SERIAL_PORT_ADDR(n)->s_r_control_bit.clkdati CLKR DATIN x Clock receive data input Data input on CLKR when configured as general-purpose input.
A write has no effect.
SERIAL_PORT_ADDR(n)->s_r_control_bit.clkdato CLKR DATOUT 0 Clock receive data output Data output on CLKR when configured as general-purpose
output.
SERIAL_PORT_ADDR(n)->s_r_control_bit.clkfunc CLKR FUNC 0 Clock receive function Controls the function of CLKR. If CLKR FUNC = 0, CLKR is configured as a general-purpose digital I/O port.If CLKR FUNC = 1, CLKR is configured as a serial port pin.
SERIAL_PORT_ADDR(n)->s_r_control_bit.clki_o CLKR I/O 0 Clock receive input/output mode If CLKR I/O = 0, CLKR is configured as a general-purpose input pin. If CLKR I/O = 1, CLKR is configured as a general-purpose output pin.
SERIAL_PORT_ADDR(n)->s_r_control_bit.ddatin DR DATIN x DR data input Data input on DR when configured as general-purpose input. A write has no effect.
SERIAL_PORT_ADDR(n)->s_r_control_bit.ddatout DR DATOUT 0 DR data output Data output on DR when configured as general-purpose output.
SERIAL_PORT_ADDR(n)->s_r_control_bit.dfunc DR FUNC 0 DR function Controls the function of DR. If DR FUNC = 0, DR is configured as a general-purpose digital I/O port. If DR FUNC = 1, DR is configured as a serial port pin.
SERIAL_PORT_ADDR(n)->s_r_control_bit.di_o DR I/O 0 DR input/output mode If DR I/O = 0, DR is configured as a general-purpose input pin. If DR I/O = 1, DR is configured as a general-purpose output pin.
SERIAL_PORT_ADDR(n)->s_r_control_bit.fsdatin FSR DATIN x FSR data input Data input on FSR when configured as general-purpose input. A write has no effect.
SERIAL_PORT_ADDR(n)->s_r_control_bit.fsdatout FSR DATOUT 0 FSR data output Data output on FSR when configured as general-purpose output.
SERIAL_PORT_ADDR(n)->s_r_control_bit.fsfunc FSR FUNC 0 FSR function FSR FUNC controls the function of FSR. If FSR FUNC = 0, FSR is configured as a general-purpose digital I/O port. If FSR FUNC = 1, FSR is configured as a serial port pin.
SERIAL_PORT_ADDR(n)->s_r_control_bit.fsi_o FSR I/O 0 FSR input/output mode If FSR I/O = 0, FSR is configured as a general-purpose input
pin. If FSR I/O = 1, FSR is configured as a general-purpose output pin.
SERIAL_PORT_ADDR(n)->s_x_control
FSX/DX/CLKX Port Control Register
   CLKXFUNC | CLKXI_O | CLKXDATOUT | CLKXDATIN | DXFUNC | DXI_O | DXDATOUT | DXDATIN | FSXFUNC | FSXI_O | FSXDATOUT | FSXDATIN
SERIAL_PORT_ADDR(n)->s_x_control_bit.clkdati CLKX DATIN x Clock transmit data input Data input on CLKX when configured as general-purpose input.
A write has no effect.
SERIAL_PORT_ADDR(n)->s_x_control_bit.clkdato CLKX DATOUT 0 Clock transmit data output Data output on CLKX when configured as general-purpose
output.
SERIAL_PORT_ADDR(n)->s_x_control_bit.clkfunc CLKX FUNC 0 Clock transmit function Controls the function of CLKX. If CLKX FUNC = 0, CLKX is configured as a general-purpose digital I/O port.If CLKX FUNC = 1, CLKX is configured as a serial port pin.
SERIAL_PORT_ADDR(n)->s_x_control_bit.clki_o CLKX I/O 0 Clock transmit input/output mode If CLK I/O = 0, CLK is configured as a general-purpose input pin. If CLK I/O = 1, CLK is configured as a general-purpose output pin.
SERIAL_PORT_ADDR(n)->s_x_control_bit.ddatin DX DATIN x DX data input Data input on DX when configured as general-purpose input. A write has no effect.
SERIAL_PORT_ADDR(n)->s_x_control_bit.ddatout DX DATOUT 0 DX data output Data output on DX when configured as general-purpose output.
SERIAL_PORT_ADDR(n)->s_x_control_bit.dfunc DX FUNC 0 DR function Controls the function of DR. If DR FUNC = 0, DR is configured as a general-purpose digital I/O port. If DR FUNC = 1, DR is configured as a serial port pin.
SERIAL_PORT_ADDR(n)->s_x_control_bit.di_o DX I/O 0 DX input/output mode If DX I/O = 0, DX is configured as a general-purpose input pin. If DX I/O = 1, DX is configured as a general-purpose output pin.
SERIAL_PORT_ADDR(n)->s_x_control_bit.fsdatin FSX DATIN x FSX data input Data input on FSX when configured as general-purpose input. A write has no effect.
SERIAL_PORT_ADDR(n)->s_x_control_bit.fsdatout FSX DATOUT 0 FSW data output Data output on FSX when configured as general-purpose output.
SERIAL_PORT_ADDR(n)->s_x_control_bit.fsfunc FSX FUNC 0 FSX function FSX FUNC controls the function of FSW. If FSW FUNC = 0, FSW is configured as a general-purpose digital I/O port. If FSW FUNC = 1, FSW is configured as a serial port pin.
SERIAL_PORT_ADDR(n)->s_x_control_bit.fsi_o FSX I/O 0 FSW input/output mode If FSX I/O = 0, FSX is configured as a general-purpose input
pin. If FSX I/O = 1, FSX is configured as a general-purpose output pin.
SERIAL_PORT_ADDR(n)->s_rxt_control
Rx/Tx
Timer Control Register
   XGO | XHLD_ | XCP_ | XCLKSRC | XTSTAT | RGO | RHLD_ | RCP_ | RCLKSRC
RSTAT
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.rclksrc RCLKSRC 0 Receive timer clock source Specifies the source of the receive timer clock. When RCLKSRC = 1, an internal clock with frequency equal to one-half the CLKOUT frequency is used to increment the counter. When RCLKSRC = 0, you can use an external signal from
the CLKR pin to increment the counter. The external clock source is synchronized internally, allowing for external asynchronous clock sources that do not exceed the speci-fied maximum allowable external clock frequency (that is, less than f(H1)/2.6).
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.rcp_ RC/P 0 Rclock/pulse mode control When RC/P = 1, the clock mode is chosen. The signaling of the status flag and external output has a 50% duty cycle. When RC/P = 0, the status flag and external output are active for one CLKOUT cycle during each timer period.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.rgo RGO 0 Receive timer counter restart Resets and starts the receive timer counter. When RGO is set to 1 and the timer is not held, the counter is zeroed and begins incrementing on the next rising edge of the timer input clock. The RGO bit is cleared on the same rising edge. Writing 0
to RGO has no effect on the receive timer.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.rhld_ RHLD 0 Receive counter hold signal If RHLD = 0, the counter is disabled and held in its current
state. If RHLD = 1, the internal divide-by-2 counter is also held so that the counter will continue where it left off. You can read and modify the timer registers while the timer is being held. RESET has priority over RHLD.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.rtstat RTSTAT 0 Receive timer status Indicates the status of the receive timer. It tracks what would be the output of the uninverted CLKR pin. This flag sets a CPU interrupt on a transition from 0 to 1. A write has no effect.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.xclksrc XCLKSRC 0 Transmit clock source Specifies the source of the transmit timer clock. When XCLKSRC = 1, an internal clock with frequency equal to one-half the CLKOUT frequency is used to increment the counter. When XCLKSRC = 0, you can use an external signal from the CLKX pin to increment the counter. The external clock source is synchronized internally, thus allowing for external asynchronous clock sources that do not exceed the specified maximum allowable external clock frequency, that is, less than f(H1)/2.6.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.xcp_ XC/P 0 Peripherals Transmit clock/pulse mode control When XC/P = 1, the clock mode is chosen. The signaling of the status flag and external output has a 50 percent duty cycle. When XC/P = 0, the status flag and external output are active for one CLKOUT cycle during each timer period.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.xgo XGO 0 Transmit timer counter restart Resets and restarts the transmit timer counter. If XGO = 1 and the timer is not held, the counter is zeroed and begins incrementing on the next rising edge of the timer input clock. The XGO bit is cleared on the same rising edge. Writing 0 to XGO has no effect on the transmit timer.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.xhld_ XHLD 0 Transmit counter hold signal If XHLD = 0, the counter is disabled and held in its current
state. If XHLD = 1, the internal divide-by-two counter is also held so that the counter continues where it left off.
SERIAL_PORT_ADDR(n)->s_rxt_control_bit.xtstat XTSTAT 0 Transmit timer status Indicates the status of the transmit timer. It tracks what would be the output of the uninverted CLKX pin. This flag sets a CPU interrupt on a transition from 0 to 1. A write has no effect.
SERIAL_PORT_ADDR(n)->s_rxt_counter Rx/Tx Counter    
SERIAL_PORT_ADDR(n)->s_rxt_counter_bit.r_counter     Receive counter
SERIAL_PORT_ADDR(n)->s_rxt_counter_bit.x_counter     Transmit counter
SERIAL_PORT_ADDR(n)->s_rxt_period Rx/Tx Period    
SERIAL_PORT_ADDR(n)->s_rxt_period_bit.r_period     Receive period
SERIAL_PORT_ADDR(n)->s_rxt_period_bit.x_period     Transmit period
SERIAL_PORT_ADDR(n)->r_data Rx Data    
SERIAL_PORT_ADDR(n)->x_data Tx Data    

Timer-Control Registers

Registre
 Désignation
Reset Value
Valeurs
TIMER_ADDR(n)->gcontrol
Timer Control Register
   FUNC | I_O | DATOUT | DATIN | GO | HLD_ | CP_ | CLKSRC | INV | TSTAT
TIMER_ADDR(n)->gcontrol_bit.clksrc CLKSRC 0 Clock source This bit specifies the source of the timer clock. When CLKSRC = 1, an internal clock with a frequency equal to one-half of the H1 frequency is used to increment the counter. The INV bit has no effect on the internal clock source. When CLKSRC = 0, you can use an external signal from the TCLK pin to increment the counter. The external clock is synchronized internally, thus allowing external asynchronous clock sources that do not exceed the specified maximum allowable external clock frequency. This is less than f(H1)/2.
TIMER_ADDR(n)->gcontrol_bit.cp_ C/P 0 Clock/pulse mode control When C/P = 1, clock mode is chosen, and the signaling of the TSTAT flag and external output has a 50% duty cycle. When C/P = 0, the status flag and external output will be active for one H1 cycle during each timer period (see Figure 12–4 on page 12-8).
TIMER_ADDR(n)->gcontrol_bit.datin DATIN x Data input Data input on TCLK or DATOUT. A write has no effect.
TIMER_ADDR(n)->gcontrol_bit.datout DATOUT 0 Data output Drives TCLK when the ’C3x is in I/O port mode. You can use DATOUT as an input to the timer.
TIMER_ADDR(n)->gcontrol_bit.func FUNC 0 Function Controls the function of TCLK. If FUNC = 0, TCLK is configured as a general-purpose digital I/O port. If FUNC = 1, TCLK is configured as a timer pin.
TIMER_ADDR(n)->gcontrol_bit.go GO 0 Go Resets and starts the timer counter. When GO = 1 and the timer is not held, the counter is zeroed and
begins incrementing on the next rising edge of the timer input clock. The GO bit is cleared on the same rising edge. GO = 0 has no effect on the timer.
TIMER_ADDR(n)->gcontrol_bit.hld_ HLD 0 Counter hold signal When this bit is 0, the counter is disabled and held in its current state. If the timer is driving TCLK, the state of TCLK is also held. The internal divide-by-2 counter is also held so that the counter can continue where it left off when HLD is set to 1. You can read and modify the timer registers while the timer is being held. RESET has priority over HLD. The effect of writing to GO and HOLD is shown below.
GO=0 HLD=0 All timer operations are held. No reset is performed (reset value).
GO=0 HLD=1 Timer proceeds from state before write.
GO=1 HLD=0 All timer operations are held, including zeroing of the counter. The GO bit is not cleared until the timer is taken out of hold.
GO=1 HLD=1 Timer resets and starts.
TIMER_ADDR(n)->gcontrol_bit.inv INV 0 Inverter control bit If an external clock source is used and INV = 1, the external clock is inverted as it goes into the counter. If the output of the pulse generator is routed to TCLK and INV = 1, the output is inverted before it goes to TCLK (see Figure 12–1 on page 12-2). If INV = 0, no inversion is performed on the input or output of the timer. The INV bit has no effect, regard-less of its value, when TCLK is used in I/O port mode.
TIMER_ADDR(n)->gcontrol_bit.i_o I/O 0 Input/output If FUNC = 0 and CLKSRC = 0, TCLK is configured as a general-purpose I/O pin. If I/O = 0, TCLK is configured as a general-purpose input pin. If I/O = 1, TCLK is configured as a general-purpose output pin.
TIMER_ADDR(n)->gcontrol_bit.tstat TSTAT 0 Timer status bit This bit indicates the status of the timer. It tracks the output of the uninverted TCLK pin. This flag sets a CPU interrupt on a transition from 0 to 1. A write has no effect.
TIMER_ADDR(n)->counter     Timer Counter
TIMER_ADDR(n)->period     Timer Period

IT (ne fonctionne que pour le Small Memory Model)

Macros :

GETVECT(it), retourne l'adresse de la routine correspondant à it
SETVECT(it,add), associe une routine d'it (add)à it
ENABLE(it), active cette it dans le registre IE (pour le CPU)
DISABLE(it), désactive cette it dans le registre IE (pour le CPU)
ENABLE_DMA(it), active cette it dans le registre IE (pour la synchro DMA)
DISABLE_DMA(it), désactive cette it dans le registre IE (pour la synchro DMA)

 

Liste des it pour GETVECT et SETVECT

Constante
Fonction
INT_EXT0 Interruption Externe 0 (utilisée par le Kernel)
INT_EXT1 Interruption Externe 1
INT_EXT2 Interruption Externe 2
INT_EXT3 Interruption Externe 3
INT_XINT0 Emission terminée sur Port série 0
INT_RINT0 Reception terminée sur Port série 0
INT_TINT0 Interruption Timer 0
INT_TINT1 Interruption Timer 1
INT_DINT Interruption DMA

INT_TRAP0
...
INT_TRAP31

 Trap logiciel

 

Liste des it pour ENABLE et DISABLE

Constante
It activée/désactivée
IT_EXT0 Interruption Externe 0 (utilisée par le Kernel)
IT_EXT1 Interruption Externe 1
IT_EXT2 Interruption Externe 2
IT_EXT3 Interruption Externe 3
IT_XINT0 Emission terminée sur Port série 0
IT_RINT0 Reception terminée sur Port série 0
IT_TINT0 Interruption Timer 0
IT_TINT1 Interruption Timer 1
IT_DINT Interruption DMA